Mr. Jeyenth Vijayaraghavan

Jeyenth Vijayaraghavan is a veteran technology leader with over 25 years of experience in ASIC and FPGA design and verification. Currently serving as ASIC IP Head at Ericsson India, he leads the development of cutting‑edge semiconductor solutions, driving innovation and execution excellence.

Previously, Jey held senior leadership roles at Intel, Altera, AMD, Microchip, and Cypress Semiconductor, where he managed diverse teams across digital and mixed‑signal verification, transceiver/memory interface IP, Ethernet IP, and SOC verification. His career highlights include building teams from the ground up, introducing out‑of‑the‑box solutions, and solving complex delivery challenges with a strong focus on quality.

A recognized engineering management and leadership expert, Jey is also a passionate advocate for Great Place to Work (GPTW) practices and a diversity & inclusion champion. His technical forte lies in digital and mixed‑signal verification, and he has consistently driven organizations toward excellence in semiconductor innovation.

Jey holds a Master of Science in VLSI from Wright State University and is known for his ability to combine deep technical expertise with strategic leadership, making him a trusted figure in the global semiconductor industry.